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作者：北京廣利核系統工程有限公司 董玲玲，許先音，李夢林

摘要：基于FPGA開發的核電數字化儀控系統（DCS）應用環境苛刻，功能性的故障可能引起誤操作，進而引發災難性的后果，因此對FPGA開發的軟件功能的測試尤為重要。傳統的界面仿真測試驗證效率低、可重用性差，而采用驗證方法學的驗證平臺的搭建又較為繁瑣，用時較多，不能滿足項目時間的要求。本文提出一種基于System Verilog 搭建的可重用的驗證平臺，采用虛擬端口方法模擬外部芯片接口的功能，最后采用批處理的方式開啟驗證平臺，實現自動化的仿真測試，其接口模型、算法庫及驗證平臺自啟動的框架可在不同的項目測試
中使用，實現可重用性。該平臺已在公司的核電站儀控系統產品的驗證中得到成功應用，縮短了測試時間，并滿足安全級產品認證的要求。

關鍵詞：驗證平臺；System Verilog；重用性；仿真驗證

Abstract: The application environment of the nuclear power digital instrument control system (DCS) developed by FPGA is harsh. Functional failure may cause misoperation,which may lead to disastrous consequences. Therefore it is particularly important to perform functional tests of the software developed by FPGA. The traditional interface simulation test verification efficiency is low and the reusability is poor, while the methodology-based verification platform is a bit complicated and takes a lot of time, which cannot meet the requirements of project time. In this paper, a reusable verification platform based on System Verilog is proposed. By using the method of virtual port to simulate the function of external chip, the verification platform is opened by batch processing to realize automatic simulation test. The verification platform can be used in different project tests to realize reusability. The platform has been successfully applied in the verification of the company's nuclear power plant control system products, which shortens the test time and meets the requirements of safety level product certification.

Key words: Testbench; System Verilog; Reusable; Simulation verification

在線預覽：一種可重用的驗證平臺在核電FPGA仿真測試中的應用

摘自《自動化博覽》2019年12月刊